Libav 0.7.1
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00001 /* 00002 * Copyright (C) 2003 David S. Miller <davem@redhat.com> 00003 * 00004 * This file is part of Libav. 00005 * 00006 * Libav is free software; you can redistribute it and/or 00007 * modify it under the terms of the GNU Lesser General Public 00008 * License as published by the Free Software Foundation; either 00009 * version 2.1 of the License, or (at your option) any later version. 00010 * 00011 * Libav is distributed in the hope that it will be useful, 00012 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00014 * Lesser General Public License for more details. 00015 * 00016 * You should have received a copy of the GNU Lesser General Public 00017 * License along with Libav; if not, write to the Free Software 00018 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 00019 */ 00020 00021 /* You may be asking why I hard-code the instruction opcodes and don't 00022 * use the normal VIS assembler mnenomics for the VIS instructions. 00023 * 00024 * The reason is that Sun, in their infinite wisdom, decided that a binary 00025 * using a VIS instruction will cause it to be marked (in the ELF headers) 00026 * as doing so, and this prevents the OS from loading such binaries if the 00027 * current cpu doesn't have VIS. There is no way to easily override this 00028 * behavior of the assembler that I am aware of. 00029 * 00030 * This totally defeats what libmpeg2 is trying to do which is allow a 00031 * single binary to be created, and then detect the availability of VIS 00032 * at runtime. 00033 * 00034 * I'm not saying that tainting the binary by default is bad, rather I'm 00035 * saying that not providing a way to override this easily unnecessarily 00036 * ties people's hands. 00037 * 00038 * Thus, we do the opcode encoding by hand and output 32-bit words in 00039 * the assembler to keep the binary from becoming tainted. 00040 */ 00041 00042 #ifndef AVCODEC_SPARC_VIS_H 00043 #define AVCODEC_SPARC_VIS_H 00044 00045 #define vis_opc_base ((0x1 << 31) | (0x36 << 19)) 00046 #define vis_opf(X) ((X) << 5) 00047 #define vis_sreg(X) (X) 00048 #define vis_dreg(X) (((X)&0x1f)|((X)>>5)) 00049 #define vis_rs1_s(X) (vis_sreg(X) << 14) 00050 #define vis_rs1_d(X) (vis_dreg(X) << 14) 00051 #define vis_rs2_s(X) (vis_sreg(X) << 0) 00052 #define vis_rs2_d(X) (vis_dreg(X) << 0) 00053 #define vis_rd_s(X) (vis_sreg(X) << 25) 00054 #define vis_rd_d(X) (vis_dreg(X) << 25) 00055 00056 #define vis_ss2s(opf,rs1,rs2,rd) \ 00057 __asm__ volatile (".word %0" \ 00058 : : "i" (vis_opc_base | vis_opf(opf) | \ 00059 vis_rs1_s(rs1) | \ 00060 vis_rs2_s(rs2) | \ 00061 vis_rd_s(rd))) 00062 00063 #define vis_dd2d(opf,rs1,rs2,rd) \ 00064 __asm__ volatile (".word %0" \ 00065 : : "i" (vis_opc_base | vis_opf(opf) | \ 00066 vis_rs1_d(rs1) | \ 00067 vis_rs2_d(rs2) | \ 00068 vis_rd_d(rd))) 00069 00070 #define vis_ss2d(opf,rs1,rs2,rd) \ 00071 __asm__ volatile (".word %0" \ 00072 : : "i" (vis_opc_base | vis_opf(opf) | \ 00073 vis_rs1_s(rs1) | \ 00074 vis_rs2_s(rs2) | \ 00075 vis_rd_d(rd))) 00076 00077 #define vis_sd2d(opf,rs1,rs2,rd) \ 00078 __asm__ volatile (".word %0" \ 00079 : : "i" (vis_opc_base | vis_opf(opf) | \ 00080 vis_rs1_s(rs1) | \ 00081 vis_rs2_d(rs2) | \ 00082 vis_rd_d(rd))) 00083 00084 #define vis_d2s(opf,rs2,rd) \ 00085 __asm__ volatile (".word %0" \ 00086 : : "i" (vis_opc_base | vis_opf(opf) | \ 00087 vis_rs2_d(rs2) | \ 00088 vis_rd_s(rd))) 00089 00090 #define vis_s2d(opf,rs2,rd) \ 00091 __asm__ volatile (".word %0" \ 00092 : : "i" (vis_opc_base | vis_opf(opf) | \ 00093 vis_rs2_s(rs2) | \ 00094 vis_rd_d(rd))) 00095 00096 #define vis_d12d(opf,rs1,rd) \ 00097 __asm__ volatile (".word %0" \ 00098 : : "i" (vis_opc_base | vis_opf(opf) | \ 00099 vis_rs1_d(rs1) | \ 00100 vis_rd_d(rd))) 00101 00102 #define vis_d22d(opf,rs2,rd) \ 00103 __asm__ volatile (".word %0" \ 00104 : : "i" (vis_opc_base | vis_opf(opf) | \ 00105 vis_rs2_d(rs2) | \ 00106 vis_rd_d(rd))) 00107 00108 #define vis_s12s(opf,rs1,rd) \ 00109 __asm__ volatile (".word %0" \ 00110 : : "i" (vis_opc_base | vis_opf(opf) | \ 00111 vis_rs1_s(rs1) | \ 00112 vis_rd_s(rd))) 00113 00114 #define vis_s22s(opf,rs2,rd) \ 00115 __asm__ volatile (".word %0" \ 00116 : : "i" (vis_opc_base | vis_opf(opf) | \ 00117 vis_rs2_s(rs2) | \ 00118 vis_rd_s(rd))) 00119 00120 #define vis_s(opf,rd) \ 00121 __asm__ volatile (".word %0" \ 00122 : : "i" (vis_opc_base | vis_opf(opf) | \ 00123 vis_rd_s(rd))) 00124 00125 #define vis_d(opf,rd) \ 00126 __asm__ volatile (".word %0" \ 00127 : : "i" (vis_opc_base | vis_opf(opf) | \ 00128 vis_rd_d(rd))) 00129 00130 #define vis_r2m(op,rd,mem) \ 00131 __asm__ volatile (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) ) 00132 00133 #define vis_r2m_2(op,rd,mem1,mem2) \ 00134 __asm__ volatile (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) ) 00135 00136 #define vis_m2r(op,mem,rd) \ 00137 __asm__ volatile (#op "\t[%0], %%f" #rd : : "r" (&(mem)) ) 00138 00139 #define vis_m2r_2(op,mem1,mem2,rd) \ 00140 __asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) ) 00141 00142 static inline void vis_set_gsr(unsigned int _val) 00143 { 00144 register unsigned int val __asm__("g1"); 00145 00146 val = _val; 00147 __asm__ volatile(".word 0xa7804000" 00148 : : "r" (val)); 00149 } 00150 00151 #define VIS_GSR_ALIGNADDR_MASK 0x0000007 00152 #define VIS_GSR_ALIGNADDR_SHIFT 0 00153 #define VIS_GSR_SCALEFACT_MASK 0x0000078 00154 #define VIS_GSR_SCALEFACT_SHIFT 3 00155 00156 #define vis_ld32(mem,rs1) vis_m2r(ld, mem, rs1) 00157 #define vis_ld32_2(mem1,mem2,rs1) vis_m2r_2(ld, mem1, mem2, rs1) 00158 #define vis_st32(rs1,mem) vis_r2m(st, rs1, mem) 00159 #define vis_st32_2(rs1,mem1,mem2) vis_r2m_2(st, rs1, mem1, mem2) 00160 #define vis_ld64(mem,rs1) vis_m2r(ldd, mem, rs1) 00161 #define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1) 00162 #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem) 00163 #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2) 00164 00165 #define vis_ldblk(mem, rd) \ 00166 do { register void *__mem __asm__("g1"); \ 00167 __mem = &(mem); \ 00168 __asm__ volatile(".word 0xc1985e00 | %1" \ 00169 : \ 00170 : "r" (__mem), \ 00171 "i" (vis_rd_d(rd)) \ 00172 : "memory"); \ 00173 } while (0) 00174 00175 #define vis_stblk(rd, mem) \ 00176 do { register void *__mem __asm__("g1"); \ 00177 __mem = &(mem); \ 00178 __asm__ volatile(".word 0xc1b85e00 | %1" \ 00179 : \ 00180 : "r" (__mem), \ 00181 "i" (vis_rd_d(rd)) \ 00182 : "memory"); \ 00183 } while (0) 00184 00185 #define vis_membar_storestore() \ 00186 __asm__ volatile(".word 0x8143e008" : : : "memory") 00187 00188 #define vis_membar_sync() \ 00189 __asm__ volatile(".word 0x8143e040" : : : "memory") 00190 00191 /* 16 and 32 bit partitioned addition and subtraction. The normal 00192 * versions perform 4 16-bit or 2 32-bit additions or subtractions. 00193 * The 's' versions perform 2 16-bit or 1 32-bit additions or 00194 * subtractions. 00195 */ 00196 00197 #define vis_padd16(rs1,rs2,rd) vis_dd2d(0x50, rs1, rs2, rd) 00198 #define vis_padd16s(rs1,rs2,rd) vis_ss2s(0x51, rs1, rs2, rd) 00199 #define vis_padd32(rs1,rs2,rd) vis_dd2d(0x52, rs1, rs2, rd) 00200 #define vis_padd32s(rs1,rs2,rd) vis_ss2s(0x53, rs1, rs2, rd) 00201 #define vis_psub16(rs1,rs2,rd) vis_dd2d(0x54, rs1, rs2, rd) 00202 #define vis_psub16s(rs1,rs2,rd) vis_ss2s(0x55, rs1, rs2, rd) 00203 #define vis_psub32(rs1,rs2,rd) vis_dd2d(0x56, rs1, rs2, rd) 00204 #define vis_psub32s(rs1,rs2,rd) vis_ss2s(0x57, rs1, rs2, rd) 00205 00206 /* Pixel formatting instructions. */ 00207 00208 #define vis_pack16(rs2,rd) vis_d2s( 0x3b, rs2, rd) 00209 #define vis_pack32(rs1,rs2,rd) vis_dd2d(0x3a, rs1, rs2, rd) 00210 #define vis_packfix(rs2,rd) vis_d2s( 0x3d, rs2, rd) 00211 #define vis_expand(rs2,rd) vis_s2d( 0x4d, rs2, rd) 00212 #define vis_pmerge(rs1,rs2,rd) vis_ss2d(0x4b, rs1, rs2, rd) 00213 00214 /* Partitioned multiply instructions. */ 00215 00216 #define vis_mul8x16(rs1,rs2,rd) vis_sd2d(0x31, rs1, rs2, rd) 00217 #define vis_mul8x16au(rs1,rs2,rd) vis_ss2d(0x33, rs1, rs2, rd) 00218 #define vis_mul8x16al(rs1,rs2,rd) vis_ss2d(0x35, rs1, rs2, rd) 00219 #define vis_mul8sux16(rs1,rs2,rd) vis_dd2d(0x36, rs1, rs2, rd) 00220 #define vis_mul8ulx16(rs1,rs2,rd) vis_dd2d(0x37, rs1, rs2, rd) 00221 #define vis_muld8sux16(rs1,rs2,rd) vis_ss2d(0x38, rs1, rs2, rd) 00222 #define vis_muld8ulx16(rs1,rs2,rd) vis_ss2d(0x39, rs1, rs2, rd) 00223 00224 /* Alignment instructions. */ 00225 00226 static inline const void *vis_alignaddr(const void *_ptr) 00227 { 00228 register const void *ptr __asm__("g1"); 00229 00230 ptr = _ptr; 00231 00232 __asm__ volatile(".word %2" 00233 : "=&r" (ptr) 00234 : "0" (ptr), 00235 "i" (vis_opc_base | vis_opf(0x18) | 00236 vis_rs1_s(1) | 00237 vis_rs2_s(0) | 00238 vis_rd_s(1))); 00239 00240 return ptr; 00241 } 00242 00243 static inline void vis_alignaddr_g0(void *_ptr) 00244 { 00245 register void *ptr __asm__("g1"); 00246 00247 ptr = _ptr; 00248 00249 __asm__ volatile(".word %2" 00250 : "=&r" (ptr) 00251 : "0" (ptr), 00252 "i" (vis_opc_base | vis_opf(0x18) | 00253 vis_rs1_s(1) | 00254 vis_rs2_s(0) | 00255 vis_rd_s(0))); 00256 } 00257 00258 static inline void *vis_alignaddrl(void *_ptr) 00259 { 00260 register void *ptr __asm__("g1"); 00261 00262 ptr = _ptr; 00263 00264 __asm__ volatile(".word %2" 00265 : "=&r" (ptr) 00266 : "0" (ptr), 00267 "i" (vis_opc_base | vis_opf(0x19) | 00268 vis_rs1_s(1) | 00269 vis_rs2_s(0) | 00270 vis_rd_s(1))); 00271 00272 return ptr; 00273 } 00274 00275 static inline void vis_alignaddrl_g0(void *_ptr) 00276 { 00277 register void *ptr __asm__("g1"); 00278 00279 ptr = _ptr; 00280 00281 __asm__ volatile(".word %2" 00282 : "=&r" (ptr) 00283 : "0" (ptr), 00284 "i" (vis_opc_base | vis_opf(0x19) | 00285 vis_rs1_s(1) | 00286 vis_rs2_s(0) | 00287 vis_rd_s(0))); 00288 } 00289 00290 #define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd) 00291 00292 /* Logical operate instructions. */ 00293 00294 #define vis_fzero(rd) vis_d( 0x60, rd) 00295 #define vis_fzeros(rd) vis_s( 0x61, rd) 00296 #define vis_fone(rd) vis_d( 0x7e, rd) 00297 #define vis_fones(rd) vis_s( 0x7f, rd) 00298 #define vis_src1(rs1,rd) vis_d12d(0x74, rs1, rd) 00299 #define vis_src1s(rs1,rd) vis_s12s(0x75, rs1, rd) 00300 #define vis_src2(rs2,rd) vis_d22d(0x78, rs2, rd) 00301 #define vis_src2s(rs2,rd) vis_s22s(0x79, rs2, rd) 00302 #define vis_not1(rs1,rd) vis_d12d(0x6a, rs1, rd) 00303 #define vis_not1s(rs1,rd) vis_s12s(0x6b, rs1, rd) 00304 #define vis_not2(rs2,rd) vis_d22d(0x66, rs2, rd) 00305 #define vis_not2s(rs2,rd) vis_s22s(0x67, rs2, rd) 00306 #define vis_or(rs1,rs2,rd) vis_dd2d(0x7c, rs1, rs2, rd) 00307 #define vis_ors(rs1,rs2,rd) vis_ss2s(0x7d, rs1, rs2, rd) 00308 #define vis_nor(rs1,rs2,rd) vis_dd2d(0x62, rs1, rs2, rd) 00309 #define vis_nors(rs1,rs2,rd) vis_ss2s(0x63, rs1, rs2, rd) 00310 #define vis_and(rs1,rs2,rd) vis_dd2d(0x70, rs1, rs2, rd) 00311 #define vis_ands(rs1,rs2,rd) vis_ss2s(0x71, rs1, rs2, rd) 00312 #define vis_nand(rs1,rs2,rd) vis_dd2d(0x6e, rs1, rs2, rd) 00313 #define vis_nands(rs1,rs2,rd) vis_ss2s(0x6f, rs1, rs2, rd) 00314 #define vis_xor(rs1,rs2,rd) vis_dd2d(0x6c, rs1, rs2, rd) 00315 #define vis_xors(rs1,rs2,rd) vis_ss2s(0x6d, rs1, rs2, rd) 00316 #define vis_xnor(rs1,rs2,rd) vis_dd2d(0x72, rs1, rs2, rd) 00317 #define vis_xnors(rs1,rs2,rd) vis_ss2s(0x73, rs1, rs2, rd) 00318 #define vis_ornot1(rs1,rs2,rd) vis_dd2d(0x7a, rs1, rs2, rd) 00319 #define vis_ornot1s(rs1,rs2,rd) vis_ss2s(0x7b, rs1, rs2, rd) 00320 #define vis_ornot2(rs1,rs2,rd) vis_dd2d(0x76, rs1, rs2, rd) 00321 #define vis_ornot2s(rs1,rs2,rd) vis_ss2s(0x77, rs1, rs2, rd) 00322 #define vis_andnot1(rs1,rs2,rd) vis_dd2d(0x68, rs1, rs2, rd) 00323 #define vis_andnot1s(rs1,rs2,rd) vis_ss2s(0x69, rs1, rs2, rd) 00324 #define vis_andnot2(rs1,rs2,rd) vis_dd2d(0x64, rs1, rs2, rd) 00325 #define vis_andnot2s(rs1,rs2,rd) vis_ss2s(0x65, rs1, rs2, rd) 00326 00327 /* Pixel component distance. */ 00328 00329 #define vis_pdist(rs1,rs2,rd) vis_dd2d(0x3e, rs1, rs2, rd) 00330 00331 #endif /* AVCODEC_SPARC_VIS_H */