LLVM(1)

NAME
LLVM - manual page for LLVM (http://llvm.org/):

DESCRIPTION
USAGE: cpp11-migrate [options] <source0> [... <sourceN>]

  OPTIONS:

-add-override - Make use of override specifier where possible

-asm-verbose - Add comments to directives.

-bounds-checking-single-trap - Use one trap block per function

-cppfname=<function name> - Specify the name of the generated function

-cppfor=<string> - Specify the name of the thing to generate

-cppgen - Choose what kind of output to generate

=program
    - Generate a complete program

=module
    - Generate a module definition

=contents
    - Generate contents of a module

=function
    - Generate a function definition

=functions
    - Generate all function definitions

=inline
    - Generate an inline function

=variable
    - Generate a variable definition

=type
    - Generate a type definition

-disable-spill-fusing - Disable fusing of spill code into instructions

    Choose driver interface:

-drvnvcl - Nvidia OpenCL driver

-drvcuda - Nvidia CUDA driver

-drvtest - Plain Test

-enable-correct-eh-support - Make the -lowerinvoke pass insert expensive, but correct, EH code

-enable-load-pre -

-enable-objc-arc-opts - enable/disable all ARC Optimizations

-enable-tbaa -

-fatal-assembler-warnings - Consider warnings as error

-fdata-sections - Emit data into separate sections

-ffunction-sections - Emit functions into separate sections

-final-syntax-check - Check for correct syntax after applying transformations

-help - Display available options (-help-hidden for more)

-internalize-public-api-file=<filename> - A file containing list of symbol names to preserve

-internalize-public-api-list=<list> - A list of symbol names to preserve

-join-liveintervals - Coalesce copies (default=true)

-limit-float-precision=<uint> - Generate low-precision inline sequences for some float libcalls

-loop-convert - Make use of range-based for loops where possible

-mc-x86-disable-arith-relaxation - Disable relaxation of arithmetic instruction for X86

-mips16-hard-float - MIPS: mips16 hard float enable.

-msp430-hwmult-mode - Hardware multiplier use mode

=no - Do not use hardware multiplier

=interrupts
    - Assume hardware multiplier can be used inside interrupts

=use
    - Assume hardware multiplier cannot be used inside interrupts

-nvptx-emit-line-numbers - NVPTX Specific: Emit Line numbers even without -G

-nvptx-emit-src - NVPTX Specific: Emit source line in ptx file

-nvptx-fma-level=<int>                       - NVPTX Specific: FMA contraction (0: don't do it 1: do it
    2: do it aggressively

-nvptx-mad-enable - NVPTX Specific: Enable generating FMAD instructions

-nvptx-prec-divf32=<int> - NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use IEEE Compliant F32 div.rnd if avaiable.

-nvptx-sched4reg - NVPTX Specific: schedule for register pressue

-nvvm-reflect-enable - NVVM reflection, enabled by default

-nvvm-reflect-list=<name=<int>> - A list of string=num assignments

-p=<string> - Build path

-pre-RA-sched - Instruction schedulers available (before register allocation):

=vliw-td
    - VLIW scheduler

=list-ilp
    - Bottom-up register pressure aware list scheduling which tries to balance ILP and register pressure

=list-hybrid
    - Bottom-up register pressure aware list scheduling which tries to balance latency and register pressure

=source
    - Similar to list-burr but schedules in source order when possible

=list-burr
    - Bottom-up register reduction list scheduling

=linearize
    - Linearize DAG, no scheduling

=fast
    - Fast suboptimal list scheduling

=default
    - Best scheduler for the target

-print-after-all - Print IR after each pass

-print-before-all - Print IR before each pass

-print-machineinstrs=<pass-name> - Print machine instrs

-profile-estimator-loop-weight=<loop-weight> - Number of loop executions used for profile-estimator

-profile-file=<filename> - Profile file loaded by -profile-metadata-loader

-profile-info-file=<filename> - Profile file loaded by -profile-loader

-profile-verifier-noassert - Disable assertions

-regalloc - Register allocator to use

=default
    - pick register allocator based on -O option

=basic
    - basic register allocator

=fast
    - fast register allocator

=greedy
    - greedy register allocator

=pbqp
    - PBQP register allocator

-risk - Select a maximum risk level:

=safe
    - Only safe transformations

=reasonable
    - Enable transformations that might change semantics (default)

=risky
    - Enable transformations that are likely to change semantics

-shrink-wrap - Shrink wrap callee-saved register spills/restores

-spiller - Spiller to use: (default: standard)

=trivial
    - trivial spiller

=inline
    - inline spiller

-stats - Enable statistics output from program (available with Asserts)

-struct-path-tbaa -

-summary - Print transform summary

-time-passes - Time each pass, printing elapsed time for each on exit

-use-auto - Use of 'auto' type specifier

-use-nullptr - Make use of nullptr keyword where possible

-user-null-macros=<string> - Comma-separated list of user-defined macro names that behave like NULL

-vectorize-loops - Run the Loop vectorization passes

-vectorize-slp - Run the SLP vectorization passes

-vectorize-slp-aggressive - Run the BB vectorization passes

-verify-dom-info - Verify dominator info (time consuming)

-verify-loop-info - Verify loop info (time consuming)

-verify-regalloc - Verify during register allocation

-verify-region-info - Verify region info (time consuming)

-verify-scev - Verify ScalarEvolution's backedge taken counts (slow)

-version - Display the version of this program

-x86-asm-syntax - Choose style of code to emit from X86 backend:

=att
    - Emit AT&T-style assembly

=intel
    - Emit Intel-style assembly

-x86-early-ifcvt - Enable early if-conversion on X86

-x86-use-vzeroupper - Minimize AVX to SSE transition penalty

    LLVM version 3.3

    Optimized build. Built May 7 2013 (21:07:59). Default target: x86_64-pc-linux-gnu Host CPU: corei7-avx

SEE ALSO
The full documentation for LLVM is maintained as a Texinfo manual. If the info and LLVM programs are properly installed at your site, the command

    info LLVM

should give you access to the complete manual.